Field of the Invention
The present invention relates to an imaging device including two substrates.
Description of Related Art
Imaging devices including two substrates are known (for example, see Japanese Unexamined Patent Application, First Publication No. 2011-159958). Surfaces of the two substrates face and are adhered to each other. A plurality of pixels outputting pixel signals according to incident light are arranged in one of the two substrates. A signal transfer section configured to transfer pixel signals output from the plurality of pixels on the other of the two substrates and a signal-processing circuit configured to process transferred pixel signals are arranged on the other of the two substrates.
FIG. 5 shows an example of a configuration of an imaging device including two substrates. The imaging device shown in FIG. 5 includes a first substrate 40, a second substrate 50, and a connection section configured to connect the two substrates.
A pixel section 400 and connection nodes 600 and 601 are arranged on the first substrate 40. The pixel section 400 includes a plurality of pixels arranged in a matrix form outputting pixel signals according to incident light. The plurality of pixels output pixel signals to every row of an arrangement of the plurality of pixels. In other words, pixels in the same row simultaneously output pixel signals, and pixels in different rows output pixel signals at different timings.
Operations of the plurality of pixels are controlled by pixel control signals supplied from the second substrate 50. The pixel control signals are common signals for every row, in which states of pixel control signals supplied to pixels in the same row change at the same timing and states of pixel control signals supplied to pixels in different rows change at different timings. The pixel control signals include row selection signals which sequentially select rows in which pixels outputting pixel signals are arranged. Pixels in the same row selected by the row selection signals simultaneously output pixel signals.
The plurality of connection nodes 600 are arranged in the pixel section 400. Each of the connection nodes 600 is arranged at a position of one of the pixels. In other words, the plurality of connection nodes 600 are arranged in a matrix form. The number of rows in an arrangement of the plurality of connection nodes 600 is equal to the number of rows in an arrangement of the plurality of pixels. The number of columns in the arrangement of the plurality of connection nodes 600 is equal to the number of columns in the arrangement of the plurality of pixels. Also, the number of connection nodes 600 is equal to the number of pixels. One of the connection nodes 600 may also be shared among the plurality of pixels. The plurality of connection nodes 601 are arranged outside the pixel section 400. Each of the plurality of connection nodes 601 is arranged for one row in the arrangement of the plurality of pixels. In other words, the number of connection nodes 601 is equal to the number of rows in the arrangement of the plurality of pixels. One connection node 601 may also be arranged for each of the plurality of rows in the arrangement of the plurality of pixels. The connection nodes 600 and 601 constitute the connection section which electrically connects the first substrate 40 and the second substrate 50.
A signal transfer section 500, a block of buffers and driver's 501, a block of column-scanning circuits 502, a block of AD conversion circuits 503, a functional circuit 504, a row signal generation circuit 505, a column signal generation circuit 506, a control circuit 507, registers and counters 508, and the connection nodes 600 and 601 are arranged on the second substrate 50. The plurality of connection nodes 600 are arranged in the signal transfer section 500. The signal transfer section 500 transfers pixel signals, which are transferred to the second substrate 50 from the first substrate 40 via the connection nodes 600, to the block of buffers and drivers 501. The block of buffers and drivers 501 includes column buffers and line drivers for receiving the pixel signals. As the column-scanning circuit 502 scans a plurality of pixel columns according to column-scanning signals for scanning the plurality of pixel columns, the column-scanning circuit 502 sequentially outputs pixel signals, which are output to every row from the pixels, to every column. The AD conversion circuit 503 performs AD conversion on analog pixel signals output from the column-scanning circuit 502 and outputs digital pixel signals. The functional circuit 504 performs various types of image processing on pixel signals output from the AD conversion circuit 503 as necessary.
The row signal generation circuit 505 generates pixel control signals which include row selection signals. Pixel control signals generated by the row signal generation circuit 505 are transferred to the first substrate 40 from the second substrate 50 via the connection nodes 601 and are supplied to the pixels. The column signal generation circuit 506 generates the column-scanning signals. The control circuit 507 generates a control signal which controls the buffers and drivers 501, the AD conversion circuits 503, and the functional circuit 504.
The registers and counters 508 includes registers and counters necessary to generate signals (pixel control signals, column-scanning signals, and a control signal) by the row signal generation circuit 505, the column signal generation circuit 506, and the control circuit 507. The register stores a control value controlling a timing at which a state of each of the signals (High or Low) changes. The counter counts in synchronization with a predetermined clock and outputs a count value. The control value and the count value are output to the row signal generation circuit 505, the column signal generation circuit 506, and the control circuit 507. The row signal generation circuit 505, the column signal generation circuit 506, and the control circuit 507 change the state of each of the signals at a timing at which a count value output from the counter coincides with a control value output from the register.
FIG. 6 shows a state in which signals are transferred between two substrates. Pixel control signals S1 generated by the row signal generation circuit 505 are transferred to the first substrate 40 not shown in FIG. 6 from the second substrate 50 via the connection nodes 601 of FIG. 5 and are supplied to pixels of the pixel section 400. Also, pixel signals S2 output from pixels of the pixel section 400 are transferred to the second substrate 50 from the first substrate 40 via the connection nodes 600 of FIG. 5.
In a situation in which the number of pixels is increased and high-speed driving of the pixels is progressing, pulses of row selection signals generated by the row signal generation circuit 505 may become noise on analog pixel signals AD-converted by the AD conversion circuit 503. Also, pulses of the column-scanning signals generated by the column signal generation circuit 506 and supplied to the column-scanning circuit 502 may cause noise in the analog pixel signals AD-converted by the AD conversion circuit 503. For this reason, errors may occur in AD conversion results of the AD conversion circuit 503.
Since the column-scanning circuit 502 scans columns while pixel signals of two different rows are output from pixels, the column-scanning signals are faster than the row selection signals. For this reason, it is easier for noise due to the pulses of the column-scanning signals to influence the AD conversion results of the AD conversion circuit 503.